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85314agi-11 www.icst.com/products/hiperclocks.html rev. c may 24, 2005 1 integrated circuit systems, inc. ics85314i-11 l ow s kew , 1- to -5 d ifferential - to -2.5v/3.3v lvpecl f anout b uffer g eneral d escription the ics85314i-11 is a low skew, high perfor- mance 1-to-5 differential-to-2.5v/3.3v lvpecl fanout buffer and a member of the hiperclocks? family of high performance clock solutions from ics. the ics85314i-11 has two selectable dif- ferential clock inputs. the clk0, nclk0 and clk1, nclk1 pairs can accept most standard differential input levels. the clock enable is internally synchronized to eliminate runt clock pulses on the outputs during asynchronous assertion/ deassertion of the clock enable pin. guaranteed output and part-to-part skew characteristics make the ics85314i-11 ideal for those applications demanding well defined performance and repeatability. f eatures ? 5 differential 2.5v/3.3v lvpecl outputs ? selectable differential clkx, nclkx inputs ? clk0, nclk0 and clk1, nclk1 pairs can accept the following differential input levels: lvpecl, lvds, lvhstl, hcsl, sstl ? maximum output frequency: 700mhz ? translates any single-ended input signal to 3.3v lvpecl levels with resistor bias on nclk input ? output skew: 30ps (maximum) ? part-to-part skew: 350ps (maximum) ? propagation delay: 1.8ns (maximum) ? rms phase jitter @ 155.52mhz (12khz - 20mhz): 0.05ps (typical) ? lvpecl mode operating voltage supply range: v cc = 2.375v to 3.8v, v ee = 0v ? -40c to 85c ambient operating temperature ? available in both standard and lead-free rohs-compliant packages b lock d iagram p in a ssignment q0 nq0 q1 nq1 q2 nq2 q3 nq3 q4 nq4 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 v cc nclk_en v cc nclk1 clk1 reserved nclk0 clk0 clk_sel v ee hiperclocks? ic s ics85314i-11 20-lead tssop 6.5mm x 4.4mm x 0.92mm package body g package top view ics85314i-11 20-lead soic 7.5mm x 12.8mm x 2.3mm package body m package top view clk0 nclk0 clk1 nclk1 q0 nq0 q1 nq1 q2 nq2 q3 nq3 q4 nq4 0 1 nclk_en clk_sel d q ck 0 1
85314agi-11 www.icst.com/products/hiperclocks.html rev. c may 24, 2005 2 integrated circuit systems, inc. ics85314i-11 l ow s kew , 1- to -5 d ifferential - to -2.5v/3.3v lvpecl f anout b uffer t able 1. p in d escriptions t able 2. p in c haracteristics l o b m y sr e t e m a r a ps n o i t i d n o c t s e tm u m i n i ml a c i p y tm u m i x a ms t i n u c n i e c n a t i c a p a c t u p n i 4f p r p u l l u p r o t s i s e r p u l l u p t u p n i 1 5k r n w o d l l u p r o t s i s e r n w o d l l u p t u p n i 1 5k r e b m u ne m a ne p y tn o i t p i r c s e d 2 , 10 q n , 0 qt u p t u o. s l e v e l e c a f r e t n i l c e p v l . r i a p t u p t u o l a i t n e r e f f i d 4 , 31 q n , 1 qt u p t u o. s l e v e l e c a f r e t n i l c e p v l . r i a p t u p t u o l a i t n e r e f f i d 6 , 52 q n , 2 qt u p t u o. s l e v e l e c a f r e t n i l c e p v l . r i a p t u p t u o l a i t n e r e f f i d 8 , 73 q n , 3 qt u p t u o. s l e v e l e c a f r e t n i l c e p v l . r i a p t u p t u o l a i t n e r e f f i d 0 1 , 94 q n , 4 qt u p t u o. s l e v e l e c a f r e t n i l c e p v l . r i a p t u p t u o l a i t n e r e f f i d 1 1v e e r e w o p. n i p y l p p u s e v i t a g e n 2 1l e s _ k l ct u p n in w o d l l u p . s t u p n i 1 k l c n , 1 k l c s t c e l e s , h g i h n e h w . t u p n i t c e l e s k c o l c . s t u p n i 0 k l c n , 0 k l c s t c e l e s , w o l n e h w . s l e v e l e c a f r e t n i s o m c v l / l t t v l 3 10 k l ct u p n in w o d l l u p. t u p n i k c o l c l a i t n e r e f f i d g n i t r e v n i - n o n 4 10 k l c nt u p n ip u l l u p. t u p n i k c o l c l a i t n e r e f f i d g n i t r e v n i 5 1d e v r e s e r. t c e n n o c t o n o d 6 11 k l ct u p n in w o d l l u p. t u p n i k c o l c l a i t n e r e f f i d g n i t r e v n i - n o n 7 11 k l c nt u p n ip u l l u p. t u p n i k c o l c l a i t n e r e f f i d g n i t r e v n i 0 2 , 8 1v c c r e w o p. s n i p y l p p u s e v i t i s o p 9 1n e _ k l c nt u p n in w o d l l u p k c o l c w o l l o f s t u p t u o k c o l c , w o l n e h w . e l b a n e k c o l c g n i z i n o r h c n y s d e c r o f e r a s t u p t u o q n , w o l d e c r o f e r a s t u p t u o q , h g i h n e h w . t u p n i . s l e v e l e c a f r e t n i s o m c v l / l t t v l . h g i h : e t o n n w o d l l u p d n a p u l l u p . s e u l a v l a c i p y t r o f , s c i t s i r e t c a r a h c n i p , 2 e l b a t e e s . s r o t s i s e r t u p n i l a n r e t n i o t r e f e r
85314agi-11 www.icst.com/products/hiperclocks.html rev. c may 24, 2005 3 integrated circuit systems, inc. ics85314i-11 l ow s kew , 1- to -5 d ifferential - to -2.5v/3.3v lvpecl f anout b uffer t able 3a. c ontrol i nput f unction t able t able 3b. c lock i nput f unction t able s t u p n is t u p t u o n e _ k l c nl e s _ k l ce c r u o s d e t c e l e s4 q : 0 q4 q n : 0 q n 00 0 k l c n , 0 k l cd e l b a n ed e l b a n e 01 1 k l c n , 1 k l cd e l b a n ed e l b a n e 10 0 k l c n , 0 k l cw o l ; d e l b a s i dh g i h ; d e l b a s i d 11 1 k l c n , 1 k l cw o l ; d e l b a s i dh g i h ; d e l b a s i d e g d e k c o l c t u p n i g n i l l a f a g n i w o l l o f d e l b a n e r o d e l b a s i d e r a s t u p t u o k c o l c e h t , s e h c t i w s n e _ k l c n r e t f a . 1 e r u g i f n i n w o h s s a s t u p n i 1 k l c n , 1 k l c d n a 0 k l c n , 0 k l c e h t f o n o i t c n u f a e r a s t u p t u o e h t f o e t a t s e h t , e d o m e v i t c a e h t n i . b 3 e l b a t n i d e b i r c s e d s a s t u p n is t u p t u o e d o m t u p t u o o t t u p n iy t i r a l o p 1 k l c r o 0 k l c1 k l c n r o 0 k l c n4 q : 0 q4 q n : 0 q n 01w o lh g i hl a i t n e r e f f i d o t l a i t n e r e f f i dg n i t r e v n i n o n 10 h g i hw o ll a i t n e r e f f i d o t l a i t n e r e f f i dg n i t r e v n i n o n f igure 1. nclk_en t iming d iagram enabled disabled nclk0, nclk1 clk0, clk1 nclk_en nq0:nq4 q0:q4
85314agi-11 www.icst.com/products/hiperclocks.html rev. c may 24, 2005 4 integrated circuit systems, inc. ics85314i-11 l ow s kew , 1- to -5 d ifferential - to -2.5v/3.3v lvpecl f anout b uffer t able 4a. p ower s upply dc c haracteristics , v cc = 2.375v to 3.8v, v ee = 0v, t a = -40c to 85c t able 4b. lvcmos / lvttl dc c haracteristics , v cc = 2.375v to 3.8v, v ee = 0v, t a = -40c to 85c l o b m y sr e t e m a r a ps n o i t i d n o c t s e tm u m i n i ml a c i p y tm u m i x a ms t i n u v h i e g a t l o v h g i h t u p n il e s _ k l c , n e _ k l c n2v c c 3 . 0 +v v l i e g a t l o v w o l t u p n il e s _ k l c , n e _ k l c n3 . 0 -8 . 0v i h i t n e r r u c h g i h t u p n in e _ k l c n , l e s _ k l cv n i v = c c v 8 . 3 =0 5 1a i l i t n e r r u c w o l t u p n in e _ k l c n , l e s _ k l cv c c v , v 8 . 3 = n i v 0 =5 -a l o b m y sr e t e m a r a ps n o i t i d n o c t s e tm u m i n i ml a c i p y tm u m i x a ms t i n u v c c e g a t l o v y l p p u s r e w o p 5 7 3 . 23 . 38 . 3v i e e t n e r r u c y l p p u s r e w o p 0 8a m t able 4c. d ifferential dc c haracteristics , v cc = 2.375v to 3.8v, v ee = 0v, t a = -40c to 85c l o b m y sr e t e m a r a ps n o i t i d n o c t s e tm u m i n i ml a c i p y tm u m i x a ms t i n u i h i t n e r r u c h g i h t u p n i 1 k l c n , 0 k l c nv c c v = n i v 8 . 3 =0 5 1a 1 k l c , 0 k l cv c c v = n i v 8 . 3 =0 5 1a i l i t n e r r u c w o l t u p n i 1 k l c n , 0 k l c nv c c v , v 8 . 3 = n i v 0 =0 5 1 -a 1 k l c , 0 k l cv c c v , v 8 . 3 = n i v 0 =5 -a v p p e g a t l o v t u p n i k a e p - o t - k a e p 5 1 . 03 . 1v v r m c ; e g a t l o v t u p n i e d o m n o m m o c 2 , 1 e t o n 5 . 0v c c 5 8 . 0 -v v s i x k l c n , x k l c r o f e g a t l o v t u p n i m u m i x a m e h t s n o i t a c i l p p a d e d n e e l g n i s r o f : 1 e t o n c c . v 3 . 0 + v s a d e n i f e d s i e g a t l o v e d o m n o m m o c : 2 e t o n h i . a bsolute m aximum r atings supply voltage, v cc 4.6v inputs, v i -0.5v to v cc + 0.5 v outputs, i o continuous current 50ma surge current 100ma package thermal impedance, ja 73.2c/w (0 lfpm) storage temperature, t stg -65c to 150c note: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these ratings are stress specifications only. functional operation of product at these conditions or any conditions be- yond those listed in the dc characteristics or ac character- istics is not implied. exposure to absolute maximum rating conditions for extended periods may affect product reliability.
85314agi-11 www.icst.com/products/hiperclocks.html rev. c may 24, 2005 5 integrated circuit systems, inc. ics85314i-11 l ow s kew , 1- to -5 d ifferential - to -2.5v/3.3v lvpecl f anout b uffer t able 4d. lvpecl dc c haracteristics , v cc = 2.375v to 3.8v, v ee = 0v, t a = -40c to 85c t able 5. ac c haracteristics , v cc = 2.375v to 3.8v, v ee = 0v, t a = -40c to 85c l o b m y sr e t e m a r a ps n o i t i d n o c t s e tm u m i n i ml a c i p y tm u m i x a ms t i n u f x a m y c n e u q e r f t u p t u o 0 0 7z h m p t h l ; h g i h o t w o l , y a l e d n o i t a g a p o r p 1 e t o n ? z h m 0 0 70 . 14 . 18 . 1s n t ) o ( k s5 , 2 e t o n ; w e k s t u p t u o 0 3s p ) ? ( t i j t ; ) m o d n a r ( r e t t i j e s a h p s m r 4 e t o n : e g n a r n o i t a r g e t n i ) z h m 0 2 - z h k 2 1 ( 5 0 . 0s p t ) p p ( k s5 , 3 e t o n ; w e k s t r a p - o t - t r a p 0 5 3s p t s e m i t p u t e sk l c o t n e _ k l c n0 5s p t h e m i t d l o hk l c o t n e _ k l c n0 5s p t r /t f e m i t l l a f / e s i r t u p t u o% 0 8 o t % 0 20 0 20 0 7s p c d oe l c y c y t u d t u p t u o? z h m 0 0 75 45 5s p f t a d e r u s a e m s r e t e m a r a p l l a x a m . e s i w r e h t o d e t o n s s e l n u r e t t i j d d a t o n s e o d t r a p e h t . t u p t u o e h t n o r e t t i j e h t l a u q e l l i w t u p n i e h t n o r e t t i j e l c y c - o t - e l c y c e h t . t n i o p g n i s s o r c t u p t u o l a i t n e r e f f i d e h t o t t n i o p g n i s s o r c t u p n i l a i t n e r e f f i d e h t m o r f d e r u s a e m : 1 e t o n . s n o i t i d n o c d a o l l a u q e h t i w d n a e g a t l o v y l p p u s e m a s e h t t a s t u p t u o n e e w t e b w e k s s a d e n i f e d : 2 e t o n . s t n i o p s s o r c l a i t n e r e f f i d t u p t u o e h t t a d e r u s a e m s e g a t l o v y l p p u s e m a s e h t t a g n i t a r e p o s e c i v e d t n e r e f f i d n o s t u p t u o n e e w t e b w e k s s a d e n i f e d : 3 e t o n d e r u s a e m e r a s t u p t u o e h t , e c i v e d h c a e n o s t u p n i f o e p y t e m a s e h t g n i s u . s n o i t i d n o c d a o l l a u q e h t i w d n a . s t n i o p s s o r c l a i t n e r e f f i d e h t t a . t o l p e s i o n e s a h p o t r e f e r e s a e l p : 4 e t o n . 5 6 d r a d n a t s c e d e j h t i w e c n a d r o c c a n i d e n i f e d s i r e t e m a r a p s i h t : 5 e t o n l o b m y sr e t e m a r a ps n o i t i d n o c t s e tm u m i n i ml a c i p y tm u m i x a ms t i n u v h o 1 e t o n ; e g a t l o v h g i h t u p t u ov c c 4 . 1 -v c c 9 . 0 -v v l o 1 e t o n ; e g a t l o v w o l t u p t u ov c c 0 . 2 -v c c 7 . 1 -v v g n i w s g n i w s e g a t l o v t u p t u o k a e p - o t - k a e p 6 . 00 . 1v 0 5 h t i w d e t a n i m r e t s t u p t u o : 1 e t o n v o t c c . v 2 -
85314agi-11 www.icst.com/products/hiperclocks.html rev. c may 24, 2005 6 integrated circuit systems, inc. ics85314i-11 l ow s kew , 1- to -5 d ifferential - to -2.5v/3.3v lvpecl f anout b uffer t ypical p hase n oise at 155.52mh z 0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130 -140 -150 -160 -170 -180 -190 1k 10k 100k 1m 10m 100m 155.52mhz rms phase jitter (random) 12khz to 20mhz = 0.05ps (typical) o ffset f requency (h z ) n oise p ower dbc hz raw phase noise data ?
85314agi-11 www.icst.com/products/hiperclocks.html rev. c may 24, 2005 7 integrated circuit systems, inc. ics85314i-11 l ow s kew , 1- to -5 d ifferential - to -2.5v/3.3v lvpecl f anout b uffer p arameter m easurement i nformation o utput s kew d ifferential i nput l evel 3.3v o utput l oad ac t est c ircuit scope qx nqx lvpecl 2v t pd p ropagation d elay o utput r ise /f all t ime o utput d uty c ycle /p ulse w idth /p eriod -1.8v -0.375v t sk(o) nqx qx nqy qy clock outputs 20% 80% 80% 20% t r t f v sw i n g t pw t period t pw t period odc = x 100% q0:q4 nq0:nq4 v cmr cross points v pp v cc v ee clk0, clk1 nclk0, nclk1 clk0, clk1 nclk0, nclk1 q0:q4 nq0:nq4 v cc v ee
85314agi-11 www.icst.com/products/hiperclocks.html rev. c may 24, 2005 8 integrated circuit systems, inc. ics85314i-11 l ow s kew , 1- to -5 d ifferential - to -2.5v/3.3v lvpecl f anout b uffer a pplication i nformation f igure 2. s ingle e nded s ignal d riving d ifferential i nput figure 2 shows how the differential input can be wired to accept single ended levels. the reference voltage v_ref = v cc /2 is generated by the bias resistors r1, r2 and c1. this bias circuit should be located as close as possible to the input pin. the w iring the d ifferential i nput to a ccept s ingle e nded l evels ratio of r1 and r2 might need to be adjusted to position the v_ref in the center of the input voltage swing. for example, if the input clock swing is only 2.5v and v cc = 3.3v, v_ref should be 1.25v and r2/r1 = 0.609. v_ref r1 1k c1 0.1u r2 1k single ended clock input clk nclk vcc i nputs : clk i nput : for applications not requiring the use of a clock input, it can be left floating. though not required, but for additional protection, a 1k resistor can be tied from the clk input to ground. clk/nclk i nput : for applications not requiring the use of the differential input, both clk and nclk can be left floating. though not required, but for additional protection, a 1k resistor can be tied from clk to ground. lvcmos c ontrol p ins : all control pins have internal pull-ups or pull-downs; additional resistance is not required but can be added for additional protection. a 1k resistor can be used. r ecommendations for u nused i nput and o utput p ins o utputs : lvpecl o utput all unused lvpecl outputs can be left floating. we recommend that there is no trace attached. both sides of the differential output pair should either be left floating or terminated.
85314agi-11 www.icst.com/products/hiperclocks.html rev. c may 24, 2005 9 integrated circuit systems, inc. ics85314i-11 l ow s kew , 1- to -5 d ifferential - to -2.5v/3.3v lvpecl f anout b uffer f igure 3c. h i p er c lock s clk/ n clk i nput d riven by 3.3v lvpecl d river f igure 3b. h i p er c lock s clk/ n clk i nput d riven by 3.3v lvpecl d river f igure 3d. h i p er c lock s clk/ n clk i nput d riven by 3.3v lvds d river 3.3v r1 50 r3 50 zo = 50 ohm lvpecl zo = 50 ohm hiperclocks clk nclk 3.3v input r2 50 zo = 50 ohm input hiperclocks clk nclk 3.3v r3 125 r2 84 zo = 50 ohm 3.3v r4 125 lvpecl r1 84 3.3v d ifferential c lock i nput i nterface the clk /nclk accepts lvds, lvpecl, lvhstl, sstl, hcsl and other differential signals. both v swing and v oh must meet the v pp and v cmr input requirements. figures 3a to 3e show interface examples for the hiperclocks clk/nclk in- put driven by the most common driver types. the input inter- f igure 3a. h i p er c lock s clk/ n clk i nput d riven by ics h i p er c lock s lvhstl d river faces suggested here are examples only. please consult with the vendor of the driver component to confirm the driver termi- nation requirements. for example in figure 3a, the input ter- mination applies for ics hiperclocks lvhstl drivers. if you are using an lvhstl driver from another vendor, use their termination recommendation. 1.8v r2 50 input lvhstl driver ics hiperclocks r1 50 lvhstl 3.3v zo = 50 ohm zo = 50 ohm hiperclocks clk nclk f igure 3e. h i p er c lock s clk/ n clk i nput d riven by 3.3v lvpecl d river with ac c ouple zo = 50 ohm r3 125 hiperclocks clk nclk 3.3v r5 100 - 200 3.3v r2 84 3.3v r6 100 - 200 input r5,r6 locate near the driver pin. zo = 50 ohm r1 84 r4 125 c2 lvpecl c1 zo = 50 ohm r1 100 3.3v lvds_driv er zo = 50 ohm receiv er clk nclk 3.3v
85314agi-11 www.icst.com/products/hiperclocks.html rev. c may 24, 2005 10 integrated circuit systems, inc. ics85314i-11 l ow s kew , 1- to -5 d ifferential - to -2.5v/3.3v lvpecl f anout b uffer the clock layout topology shown below is a typical termi- nation for lvpecl outputs. the two different layouts men- tioned are recommended only as guidelines. fout and nfout are low impedance follower outputs that generate ecl/lvpecl compatible outputs. therefore, ter- minating resistors (dc current path to ground) or current sources must be used for functionality. these outputs are v cc - 2v 50 50 rtt z o = 50 z o = 50 fout fin rtt = z o 1 ((v oh + v ol ) / (v cc ? 2)) ? 2 3.3v 125 125 84 84 z o = 50 z o = 50 fout fin f igure 4b. lvpecl o utput t ermination f igure 4a. lvpecl o utput t ermination t ermination for 3.3v lvpecl o utputs designed to drive 50 transmission lines. matched imped- ance techniques should be used to maximize operating frequency and minimize signal distortion. figures 4a and 4b show two different layouts which are recommended only as guidelines. other suitable clock layouts may exist and it would be recommended that the board designers simulate to guarantee compatibility across all printed circuit and clock component process variations.
85314agi-11 www.icst.com/products/hiperclocks.html rev. c may 24, 2005 11 integrated circuit systems, inc. ics85314i-11 l ow s kew , 1- to -5 d ifferential - to -2.5v/3.3v lvpecl f anout b uffer t ermination for 2.5v lvpecl o utput figure 5a and figure 5b show examples of termination for 2.5v lvpecl driver. these terminations are equivalent to ter- minating 50 to v cc - 2v. for v cc = 2.5v, the v cc - 2v is very close to ground level. the r3 in figure 5b can be eliminated and the termination is shown in figure 5c. f igure 5c. 2.5v lvpecl t ermination e xample f igure 5b. 2.5v lvpecl d river t ermination e xample f igure 5a. 2.5v lvpecl d river t ermination e xample r2 62.5 zo = 50 ohm r1 250 + - 2.5v 2,5v lvpecl driv er r4 62.5 r3 250 zo = 50 ohm 2.5v vcc=2.5v r1 50 r3 18 zo = 50 ohm zo = 50 ohm + - 2,5v lvpecl driver vcc=2.5v 2.5v r2 50 2,5v lvpecl driv er vcc=2.5v r1 50 r2 50 2.5v zo = 50 ohm zo = 50 ohm + -
85314agi-11 www.icst.com/products/hiperclocks.html rev. c may 24, 2005 12 integrated circuit systems, inc. ics85314i-11 l ow s kew , 1- to -5 d ifferential - to -2.5v/3.3v lvpecl f anout b uffer p ower c onsiderations this section provides information on power dissipation and junction temperature for the ics85314i-11. equations and example calculations are also provided. 1. power dissipation. the total power dissipation for the ics85314i-11 is the sum of the core power plus the power dissipated in the load(s). the following is the power dissipation for v cc = 3.8v, which gives worst case results. note: please refer to section 3 for details on calculating power dissipated in the load. ? power (core) max = v cc_max * i ee_max = 3.8v * 80ma = 304mw ? power (outputs) max = 30.2mw/loaded output pair if all outputs are loaded, the total power is 5 * 30.2mw = 151mw total power _max (3.465v, with all outputs switching) = 304mw + 151mw = 455mw 2. junction temperature. junction temperature, tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device. the maximum recommended junction temperature for hiperclocks tm devices is 125c. the equation for tj is as follows: tj = ja * pd_total + t a tj = junction temperature ja = junction-to-ambient thermal resistance pd_total = total device power dissipation (example calculation is in section 1 above) t a = ambient temperature in order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance ja must be used. assuming a moderate air flow of 200 linear feet per minute and a multi-layer board, the appropriate value is 66.6c/w per table 6a below. therefore, tj for an ambient temperature of 85c with all outputs switching is: 85c + 0.455w * 66.6c/w = 115c. this is well below the limit of 125c. this calculation is only an example. tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow , and the type of board (single layer or multi-layer). ja by velocity (linear feet per minute) 0 200 500 single-layer pcb, jedec standard test boards 114.5c/w 98.0c/w 88.0c/w multi-layer pcb, jedec standard test boards 73. 2c/w 66.6c/w 63.5c/w note: most modern pcb designs use multi-layered boards. the data in the second row pertains to most designs. t able 6a. t hermal r esistance ja for 20- pin tssop, f orced c onvection ja by velocity (linear feet per minute) 0 200 500 single-layer pcb, jedec standard test boards 83. 2c/w 65.7c/w 57.5c/w multi-layer pcb, jedec standard test boards 46. 2c/w 39.7c/w 36.8c/w note: most modern pcb designs use multi-layered boards. the data in the second row pertains to most designs. t able 6b. t hermal r esistance ja for 20- pin soic, f orced c onvection
85314agi-11 www.icst.com/products/hiperclocks.html rev. c may 24, 2005 13 integrated circuit systems, inc. ics85314i-11 l ow s kew , 1- to -5 d ifferential - to -2.5v/3.3v lvpecl f anout b uffer 3. calculations and equations. lvpecl output driver circuit and termination are shown in figure 6. t o calculate worst case power dissipation into the load, use the following equations which assume a 50 load, and a termination voltage of v cc - 2v. ? for logic high, v out = v oh_max = v cc_max ? 1.0v (v cc_max - v oh_max ) = 1.0v ? for logic low, v out = v ol_max = v cc_max ? 1.7v (v cc_max - v ol_max ) = 1.7v pd_h is power dissipation when the output drives high. pd_l is the power dissipation when the output drives low. pd_h = [(v oh_max ? (v cc_max - 2v))/r l ] * (v cc_max - v oh_max ) = [(2v - (v cc_max - v oh_max )) /r l ] * (v cc_max - v oh_max ) = [(2v - 1v)/50 ] * 1v = 20.0mw pd_l = [(v ol_max ? (v cc_max - 2v))/r l ] * (v cc_max - v ol_max ) = [(2v - (v cc_max - v ol_max )) /r l ] * (v cc_max - v ol_max ) = [(2v - 1.7v)/50 ] * 1.7v = 10.2mw total power dissipation per output pair = pd_h + pd_l = 30.2mw f igure 6. lvpecl d river c ircuit and t ermination q1 v out v cc rl 50 v cc - 2v
85314agi-11 www.icst.com/products/hiperclocks.html rev. c may 24, 2005 14 integrated circuit systems, inc. ics85314i-11 l ow s kew , 1- to -5 d ifferential - to -2.5v/3.3v lvpecl f anout b uffer r eliability i nformation t ransistor c ount the transistor count for ics85314i-11 is: 674 compatible to part number mc100lvep14 t able 7a. ja vs . a ir f low t able for 20 l ead tssop ja by velocity (linear feet per minute) 0 200 500 single-layer pcb, jedec standard test boards 114.5c/w 98.0c/w 88.0c/w multi-layer pcb, jedec standard test boards 73. 2c/w 66.6c/w 63.5c/w note: most modern pcb designs use multi-layered boards. the data in the second row pertains to most designs. 0 200 500 single-layer pcb, jedec standard test boards 83. 2c/w 65.7c/w 57.5c/w multi-layer pcb, jedec standard test boards 46. 2c/w 39.7c/w 36.8c/w note: most modern pcb designs use multi-layered boards. the data in the second row pertains to most designs. t able 7b. ja vs . a ir f low t able for 20 l ead soic ja by velocity (linear feet per minute)
85314agi-11 www.icst.com/products/hiperclocks.html rev. c may 24, 2005 15 integrated circuit systems, inc. ics85314i-11 l ow s kew , 1- to -5 d ifferential - to -2.5v/3.3v lvpecl f anout b uffer p ackage o utline - g s uffix for 20 l ead tssop t able 8a. p ackage d imensions reference document: jedec publication 95, mo-153 l o b m y s s r e t e m i l l i m m u m i n i mm u m i x a m n0 2 a- -0 2 . 1 1 a5 0 . 05 1 . 0 2 a0 8 . 05 0 . 1 b9 1 . 00 3 . 0 c9 0 . 00 2 . 0 d0 4 . 60 6 . 6 ec i s a b 0 4 . 6 1 e0 3 . 40 5 . 4 ec i s a b 5 6 . 0 l5 4 . 05 7 . 0 0 8 a a a- -0 1 . 0
85314agi-11 www.icst.com/products/hiperclocks.html rev. c may 24, 2005 16 integrated circuit systems, inc. ics85314i-11 l ow s kew , 1- to -5 d ifferential - to -2.5v/3.3v lvpecl f anout b uffer p ackage o utline - m s uffix for 20 l ead tssop t able 8b. p ackage d imensions reference document: jedec publication 95, ms-013, mo-119 l o b m y s s r e t e m i l l i m m u m i n i mm u m i x a m n0 2 a- -5 6 . 2 1 a0 1 . 0- - 2 a5 0 . 25 5 . 2 b3 3 . 01 5 . 0 c8 1 . 02 3 . 0 d0 6 . 2 10 0 . 3 1 e0 4 . 70 6 . 7 ec i s a b 7 2 . 1 h0 0 . 0 15 6 . 0 1 h5 2 . 05 7 . 0 l0 4 . 07 2 . 1 0 8
85314agi-11 www.icst.com/products/hiperclocks.html rev. c may 24, 2005 17 integrated circuit systems, inc. ics85314i-11 l ow s kew , 1- to -5 d ifferential - to -2.5v/3.3v lvpecl f anout b uffer t able 9. o rdering i nformation while the information presented herein has been checked for both accuracy and reliability, integrated circuit systems, incorpor ated (ics) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. no other circuits, patent s, or licenses are implied. this product is intended for use in normal commercial and industrial applications. any other applications such as those requiring high reliability, or other ext raordinary environmental requirements are not recommended without additional processing by ics. ics reserves the right to change any circuitry or specifications without noti ce. ics does not authorize or warrant any ics product for use in life support devices or critical medical instruments. r e b m u n r e d r o / t r a pg n i k r a me g a k c a pg n i g a k c a p g n i p p i h se r u t a r e p m e t 1 1 - i g a 4 1 3 5 8 s c i1 1 i a 4 1 3 5 8 s c ip o s s t d a e l 0 2e b u tc 5 8 o t c 0 4 - t 1 1 - i g a 4 1 3 5 8 s c i1 1 i a 4 1 3 5 8 s c ip o s s t d a e l 0 2l e e r & e p a t 0 0 5 2c 5 8 o t c 0 4 - f l 1 1 - i g a 4 1 3 5 8 s c il 1 1 i a 4 1 3 5 s c ip o s s t " e e r f - d a e l " d a e l 0 2e b u tc 5 8 o t c 0 4 - t f l 1 1 - i g a 4 1 3 5 8 s c il 1 1 i a 4 1 3 5 s c ip o s s t " e e r f - d a e l " d a e l 0 2l e e r & e p a t 0 0 5 2c 5 8 o t c 0 4 - 1 1 - i m a 4 1 3 5 8 s c i1 1 - i a 4 1 3 5 8 s c ic i o s d a e l 0 2e b u tc 5 8 o t c 0 4 - t 1 1 - i m a 4 1 3 5 8 s c i1 1 - i a 4 1 3 5 8 s c ic i o s d a e l 0 2l e e r & e p a t 0 0 0 1c 5 8 o t c 0 4 - . t n a i l p m o c s h o r e r a d n a n o i t a r u g i f n o c e e r f - b p e h t e r a r e b m u n t r a p e h t o t x i f f u s " f l " n a h t i w d e r e d r o e r a t a h t s t r a p : e t o n the aforementioned trademark, hiperclocks is a trademark of integrated circuit systems, inc. or its subsidiaries in the united states and/or other countries.
85314agi-11 www.icst.com/products/hiperclocks.html rev. c may 24, 2005 18 integrated circuit systems, inc. ics85314i-11 l ow s kew , 1- to -5 d ifferential - to -2.5v/3.3v lvpecl f anout b uffer t e e h s y r o t s i h n o i s i v e r v e re l b a te g a pe g n a h c f o n o i t p i r c s e d e t a d a 1 t 2 t 2 2 4 7 8 d n a n o i t p i r c s e d l a i t r a p d e t e l e d , x k l c n , 7 1 & 4 1 n i p - e l b a t n o i t p i r c s e d n i p d e d d a p u l l u p n i . n m u l o c e p y t c - e l b a t s c i t s i r e t c a r a h c n i p n i . l a c i p y t f p 4 o t . x a m f p 4 d e g n a h c . g n i t a r t u p t u o d e t c e r r o c - r m a d e d d a s l e v e l d e d n e e l g n i s t p e c c a o t t u p n i l a i t n e r e f f i d e h t g n i r i w . n o i t c e s d e d d a e c a f r e t n i t u p n i k c o l c l a i t n e r e f f i d . n o i t c e s 3 0 / 1 1 / 6 b 5 t 1 5 6 8 9 . n o i t c e s s e r u t a e f n i t e l l u b e s i o n e s a h p d e d d a . r e t t i j e s a h p s m r d e d d a - e l b a t s c i t s i r e t c a r a h c c a . t o l p r e t t i j e s a h p d e d d a . s m a r g a i d t u p t u o l c e p v l v 3 . 3 r o f n o i t a n i m r e t d e t a d p u . n o i t c e s t u p t u o l c e p v l v 5 . 2 r o f n o i t a n i m r e t d e d d a 4 0 / 1 1 / 8 b 1 t 9 t 1 2 6 1 . t e l l u b e e r f - d a e l d e d d a - n o i t c e s s e r u t a e f . n o i t p i r c s e d l e s _ k l c d e t c e r r o c - e l b a t n o i t p i r c s e d n i p p o s s t r o f r e b m u n t r a p " e e r f - d a e l " d e d d a - e l b a t n o i t a m r o f n i g n i r e d r o . e g a k c a p 5 0 / 2 2 / 3 c 5 t 1 5 . x a m s p 0 5 3 o t . x a m s p 0 5 2 m o r f w e k s t r a p - o t - t r a p d e g n a h c - n o i t c e s s e r u t a e f o t . x a m s p 0 5 2 m o r f w e k s t r a p - o t - t r a p d e g n a h c - e l b a t s c i t s i r e t c a r a h c c a . x a m s p 0 5 3 5 0 / 4 2 / 5 d d 4 t5 8 v d e g n a h c - e l b a t s c i t s i r e t c a r a h c c d l c e p v l h o v m o r f x a m c c o t v 0 . 1 - v c c . v 9 . 0 - d e d d a - n o i t c e s n o i t a m r o f n i n o i t a c i l p p a t u p n i d e s u n u r o f s n o i t a d n e m m o c e r . s n i p t u p t u o d n a 5 0 / 3 2 / 9

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